HD Web
Enjoy faster Web browsing, online HD entertainment, & superb battery life with HD Web Expertise from AMD.
Virtualization
AMD has led the industry in developing features for x86-based computers that enable speedy & efficient virtualization, such as energy efficient multi-core processors, advanced memory handling capabilities, & hardware-based virtualization technologies.
Optimization for Cloud Computing
An integral part of any cloud computing surroundings is servers equipped with processors that deliver a balance of performance, I/O capabilities, low energy consumption, & hardware-assisted virtualization. AMD Opteron processors can help organizations optimize knowledge middle performance & cost-effectiveness to serve their cloud customers.
Power Efficiency
When server efficiency matters, it is not to compare spec sheets. AMD delivers power efficiency at real-world workloads. Specific power innovations include AMD Cool'n'Quiet Expertise & ATI PowerPlay, delivering proven, measurable benefits for businesses & consumers, reducing power usage, lowering energy costs & diminishing the environmental impact.
Manageability
Manage the desktops & notebooks in your network.
Security
Protect your network & knowledge.
Stability & Longevity
Manage your workload by helping reduce changes & by utilizing consistent images over multiple months.
AMD64 Expertise
The AMD64 platform led the industry to pervasive 64-bit computing.
HyperTransport Expertise
HyperTransport expertise is a high-speed, low latency, point-to-point link designed to increase the communication speed between integrated circuits in computers, servers, embedded systems, & networking & telecommunications equipment up to 48 times faster than some existing technologies.
Direct Connect Architecture
Direct Connect Architecture improves overall process performance & efficiency by eliminating traditional bottlenecks inherent in legacy front side bus architectures.
Multi-Core Processing with AMD
With the power of, or more processor cores on a single chip, AMD's true multi-core processors deliver industry-leading performance & unique features that help systems run cooler & more efficient.
*for more information, you can visit www.amd.com
Saturday, May 8, 2010
16- bit Processor Design
CAPC Processor is a 16 bit processor with main memory (RAM) of size 4,096 words, 16 bits per word. It was designed/built in LogicWorks4 for COMP212 Work (Computer Design and Architecture II) at Capilano College in the Spring2002 term. The CAPC Processor project (design/build the Processor) has been the major part of the work. This is the second version of the CAPC Processor Design Book.
- CAPC is a sequential processor with main memory (RAM) of size 4,096 words, 16 bits per word.
- It is controlled/driven by a clock, generating Fetch (5 subcycles)/Execute cycle (3 subcycles) in 8 subcycles.
- There's buses - 16 bit Information Bus for information & addresses (12 bits), & Control Bus.
- Each word, when it is used as a machine instruction, contains a five bit OP code (bits 12,13,14, & 15) & an Operand, an address (bits 0 to 11) or a constant.
- ALU unit has of input registers, U & V. It can computing ADD (U+V), AND(U^V), OR(U,V), NEG (-U) & SHR(U), shifting right 1 small bit of U.
- There's 16 bit registers; instruction register IR, & general purpose register Greg. IR is the main register to decode & execute a machine instruction.
- The 12 bit memory address register MAR is used to point the location by & massive memory. The 16 bit register MBR, memory buffer register, is used to interface with the datum into/from the main memory.
- There's addressing modes: local addressing is generated by SP+Offset, where SP is the pointer register & offset is the 12 bit address given by bit 0 to 11 of IR register. An address is contained in the memory pointed by SP+Offset. In direct addressing mode, the direct is basically given by the 12 bit, bit 0 to 11, of an operand.
- The pointer register SP could be used to simulate a Stack Pointer in programming CAPC.
- There's 16 Machine Instructions (OP codes):
| OP code bit12..15 | Instruction | Description |
| 0000 | HLT | Halt the clock signal. Operand (Bit0..11) is ignored. |
| 0001 | LOGC | Load Greg 12 bit Operand (from Bit0 to 11). |
| 0010 | LOSP | Load SP 12 bit operand (from Bit0 to 11). |
| 0011 | LOGM | Load Greg the 16 bit datum in the memory pointed by SP+Operand. |
| 0100 | SEGM | Copy the contents of Greg to the memory pointed by SP+Operand. |
8-bit Processor Design
Friday, May 7, 2010
Intel Processor's Technology
1. Enhanced Intel SpeedStep® Expertise is an advanced means of enabling very high performance while also meeting the power-conservation needs of mobile systems. Enhanced Intel SpeedStep Expertise allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (together with OS support).
2. Intel Turbo Boost Expertise feature temporarily boosts CPU performance by increasing frequency of or more cores. How much the frequency is increased depends on the number of inactive cores, i.e. cores in states C3 or C6, and how heavily active cores are utilized.
When core is active, the frequency can be increased by up to three frequency steps (266 MHz). When over core is active the frequency may be increased by frequency step (133 MHz). This feature was introduced in Core i7 microprocessor relatives.
3. Dual Dynamic Acceleration feature, which was used in older generations of quad-core processors and could boost frequency of only CPU cores, the Turbo Boost Expertise may increase frequency of all three cores.
4. Hyper-threading (HTT, officially Hyper-Threading Expertise or HT Expertise) is Intel's term for its simultaneous multithreading implementation in their Pentium 3, Atom, and Core i7 CPUs. Hyper-threading is an Intel-proprietary expertise used to improve parallelization of computations (doing multiple tasks without delay) performed on PC microprocessors. A processor with hyper-threading enabled is treated by the operating method as processors in lieu of. This means that processor is physically present but the operating method sees virtual processors, and shares the workload between them. Hyper-threading requires only that the operating method supports multiple processors, but Intel recommends disabling HT when using operating systems that have not been optimized for the expertise.
5. Execute Disable Bit is a hardware-based security feature that can reduce exposure to viruses and malicious-code assaults and prevent harmful application from executing and propagating on the server or network.
Execute Disable Bit allows memory to be marked as executable or non-executable, when combined with a supporting operating method. If code attempts to run in non-executable memory the processor raises a mistake to the operating method. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the general security of the method.
See the Intel® Architecture Application Developer's Manual for more detailed information.
2. Intel Turbo Boost Expertise feature temporarily boosts CPU performance by increasing frequency of or more cores. How much the frequency is increased depends on the number of inactive cores, i.e. cores in states C3 or C6, and how heavily active cores are utilized.
When core is active, the frequency can be increased by up to three frequency steps (266 MHz). When over core is active the frequency may be increased by frequency step (133 MHz). This feature was introduced in Core i7 microprocessor relatives.
3. Dual Dynamic Acceleration feature, which was used in older generations of quad-core processors and could boost frequency of only CPU cores, the Turbo Boost Expertise may increase frequency of all three cores.
4. Hyper-threading (HTT, officially Hyper-Threading Expertise or HT Expertise) is Intel's term for its simultaneous multithreading implementation in their Pentium 3, Atom, and Core i7 CPUs. Hyper-threading is an Intel-proprietary expertise used to improve parallelization of computations (doing multiple tasks without delay) performed on PC microprocessors. A processor with hyper-threading enabled is treated by the operating method as processors in lieu of. This means that processor is physically present but the operating method sees virtual processors, and shares the workload between them. Hyper-threading requires only that the operating method supports multiple processors, but Intel recommends disabling HT when using operating systems that have not been optimized for the expertise.
5. Execute Disable Bit is a hardware-based security feature that can reduce exposure to viruses and malicious-code assaults and prevent harmful application from executing and propagating on the server or network.
Execute Disable Bit allows memory to be marked as executable or non-executable, when combined with a supporting operating method. If code attempts to run in non-executable memory the processor raises a mistake to the operating method. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the general security of the method.
See the Intel® Architecture Application Developer's Manual for more detailed information.
Subscribe to:
Posts (Atom)